RTDS G3 imports SDL description in its textual format called SDL-PR (Phrasal Representation). Based on the CIF (Common Interchange Format) information it keeps the graphical layout as it was in the original system. The import mechanism has been tested on very large existing industrial models (more than 40,000 lines) and PragmaDev is commited to support its customers when importing legacy code.

RTDS G3 also exports SDL in textual format in order to run in any existing tool such as a test generator, exhaustive simulation tool, model checking tool, code generator.

SDL editor

SDL editor is an easy to use, intuitive interface to design SDL systems. It includes all can be expected of such an editor such as : copy/paste, unlimited undo/redo, automatic symbol insertion. The diagrams include a page setup to guarantee the final diagram will be printable. Diagrams can also be saved as PNG or JPEG files.

• It is possible to have a list of states in the state symbol,
• It is possible to have a list of inputs in the input and save symbols,
• The content of a symbol can be hidden to be edited in the text editor. The symbol will display a short cut text in the graphical editor.
  

• A partition browser eases navigation.
• XML-RPC wrappers can be automatically generated to ease SDL operators defintion in C.

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Dynamic graphical traces

The Message Sequence Chart (MSC) representation provides a detailed description of the dynamic behaviour of the system. It can be used to specify a behaviour or to trace the simulated system. Each process is seen as a line on the diagram where time flows from top to bottom. Key events in the system have a graphical representation such as: internal states modification, message inputs and outputs with structured parameters, timers, process creations or deletions... MSC diagrams can be organized using the SDL HMSC diagram.

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HMSC editor

High level Message Sequence Chart editor allows to organize MSC diagrams and define how they relate to one another: MSCs can be executed in parallel or in sequence.

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First tool on the market to support composite states

A composite state is basically a state in which one or several sub-finite state machine are running. An incoming signal is first considered by the super state. If not in the signal set the sub states are the considered. This is a concept that is found in a lot of consumer electronic MMI. A classical example is a car radio where each key has a different meaning depending on the source. The same key will switch from FM to AM when using the radio source; or it might switch to the next CD when using the CD source. The snapshots below describe this basic example.

The SDL system can be simulated with the built-in simulator based on SDL semantic to verify the system behavior. Once validated, full code can be generated with RTOS integrations to be implemented on a real target. Whether the SDL system is simulated, or whether the generated C code is debugged on target, the RTDS debugger interface will display all relevant information:

• SDL system information
  • The list of running processes,
  • The list of pending messages,
  • Re-organize the ordering of the pending messages making simulation undeterministic,
• Handle time
  • View the list of pending timers,
  • Run the system in discrete time,
  • Have a real time system behavior
• View local variables
• Watch remote variables
• Set graphical breakpoints
• Step graphically in the SDL description
• The SDL system can be simulated with undefined operators : a pop up window will then require the user to enter the return value of the operator at run time.
• The Simulator can call SDL operators defined in external libraries written in C, C++, Java, Python with the XML-RPC support.
• Connect an external tool such as a Graphical User Interface to the SDL Simulator through a socket to interact with the simulated system.

It is now possible to export an SDL System to IF form as defined by Verimag Labs.
IF is an intermediate form based on timed automatas specially designed to run mathematically based tools to explore all possible behaviors. Because it tries all possibilities, the number of explored states grows very quickly requiring strong mathematical algorythms to store the information.
Observers are associated with the SDL system in order:

• to verify a property is reached,
• to check a rule is not violated,
• to restrict the exploration space.

Verimag provides such a tool that can be downloaded from their web site. An example script for Verimag IFx tool is provided in RTDS distribution. Any other IF based tool can be easily integrated via a simple process:

• Export to IF,
• Run a script,
• Get an MSC Trace as a feedback showing how a rule has been violated.